1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method of the semiconductor device and more particularly, to a semiconductor device having a copper alloy wiring and a via connected to the copper alloy wiring and a manufacturing method of that semiconductor device.
2. Description of the Background Art
Since a multilayer wiring structure using copper having low resistance is used in a semiconductor device requiring a high speed operation and low power consumption in order to prevent a signal delay and to reduce the power consumption at a wiring part. However, as the semiconductor device is miniaturized, a current density flowing in the copper wiring is increased and reliability of the copper wiring against electromigration (referred to as the EM, hereinafter) becomes critical.
The EM is a phenomenon in which when a current flows in the copper wiring, a copper atom is pressed by the electron flow and moved. EM resistance in the contact surface between the bottom of the interlayer connection (via) connecting upper and lower wirings and the lower copper wiring is the most controversial in the copper wiring. When the EM phenomenon occurs, the copper atom in the copper wiring is moved and a void is formed in the vicinity of the contact surface of the copper wiring. Then, as a result of the void, the copper wiring and the via are electrically opened.
In order to prevent the opening between the copper wiring and the via due to the EM phenomenon, a current flowing to the copper wiring has been limited conventionally. In addition, a copper alloy wiring to which an additive element such as aluminum is added to a main component Cu has been used. Such copper alloy wiring is disclosed in non-Patent document 1 (T. Tonegawa et al (NEC), “Suppression of Bimodal Stress-Induced Voiding Using Highly Diffusive Dopant from Cu-Alloy Seed Layer”, Proceeding of IEEE International Interconnect Technology Conference 2003, pp. 216-218). EM resistance in the copper alloy wiring is superior to that in a pure copper wiring.
The non-Patent document 1 discloses a technique for improving the EM resistance by using a copper alloy wiring to which Al, Sn and Ti are added as additive elements to copper as a main component. In addition, Japanese Patent Application Laid-Open No. 2002-75995 and No. 11-307530 disclose the other techniques on the copper alloy wiring.
For example, the Japanese Patent Application Laid-Open No. 2002-75995 discloses a structure in which a copper alloy wiring and a via connected to the upper surface of the copper alloy wiring are formed in an interlayer insulation film, and a barrier metal film containing nitrogen is formed in the contact surface (can be grasped as a connection part) between the copper alloy wiring and the via.
Furthermore, the barrier metal film existing between the copper alloy wiring (including the via) and the interlayer insulation film has been also devised variously. For example, as the barrier metal film, a film having a laminated structure in which TaN, TiN, WN and the like that are highly adherent to the interlayer insulation film and Ta, Ti W and the like that are highly adherent to copper are laminated is employed (Japanese Patent Application Laid-Open No. 2003-124313)
However, in the case of the structure disclosed in the Japanese Patent Application Laid-Open No. 2002-75995, it has been found that the following problem arises from the experiment by the inventors. That is, when the barrier metal film containing nitrogen is formed on the contact surface between the copper alloy wiring and the via, the electric resistance between the copper alloy wiring and the via rises and the electric resistance varies.